Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit
US10229880B2 · kind B2 · utility
1Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2016 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Dec 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/02126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.