Semiconductor memory device including stacked chips and memory module having the same
US10229900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2017 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Sep 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory structure including a first integrated circuit chip and a plurality of second integrated circuit chips stacked on each other, the first integrated circuit chip is interposed between a pair of the plurality of second integrated circuit chips, an interface unit disposed on the first integrated circuit chip, the memory structure is connected to a third circuit through the interface unit, and the interface unit transfers operation signals to the first integrated circuit chip and the plurality of second integrated circuit chips, at least one inter-chip interconnector connected with the interface unit and the first integrated circuit chip and the plurality of second integrated circuit chips, and an external interconnector connected with the interface unit and the third circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.