Process of fabricating embedded spin transfer torque memory for cellular neural network based processing unit
US10230045B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2017 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Jul 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5329
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods for forming embedded memory in a processing unit. The methods include: depositing a dielectric layer on a metal landing pad of a logic circuit of a processing unit; opening vias in the dielectric layer; filling in the vias; performing chemical mechanical polishing (CMP); depositing an adhesion and topography planarization (ATP) layer; etching away portions of the ATP layer; filling in with inter layer dielectric (ILD) materials; performing CMP; depositing a MTJ film layer; patterning and etching away portions of the MTJ film layer; filling in with dielectric materials; performing CMP; and forming a bit line on the top layer. The methods may also include annealing in a forming gas during different steps of the above processed to reduce the high stress from the making of multi-metal layers of the processing unit at high temperature. This may prevent wafer warpage and/or significant topography in the fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.