Time-to-digital converter and digital phase locked loop
US10230383B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2017 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Aug 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time-to-digital converter including N stages of converting circuits, where N≥2, and N is an integer. Each stage of converting circuit includes a first delayer and an arbiter; an output end of the first delayer in each stage of converting circuit outputs a delayed signal of the stage of converting circuit; and the arbiter in each stage of converting circuit receives a sampling clock and the delayed signal of the stage of converting circuit, and compares the sampling clock with the delayed signal to obtain an output signal of the stage of converting circuit. Output signals of the N stages of converting circuits form a non-linear binary number, to indicate a time difference between a clock signal and a reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.