Executing a selected sequence of instructions depending on packet type in an exact-match flow switch
US10230638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2018 |
| Grant date | Mar 12, 2019 |
| Priority date | — |
| Expiry date | Jul 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/7452
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a processor and an exact-match flow table structure. A first packet is received onto the integrated circuit. The packet is determined to be of a first type. As a result of this determination, execution by the processor of a first sequence of instructions is initiated. This execution causes bits of the first packet to be concatenated and modified in a first way, thereby generating a first Flow Id. The first Flow Id is an exact-match for the Flow Id of a first stored flow entry. A second packet is received. It is of a first type. As a result, a second sequence of instructions is executed. This causes bits of the second packet to be concatenated and modified in a second way, thereby generating a second Flow Id. The second Flow Id is an exact-match for the Flow Id of a second stored flow entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.