Method for reducing threading dislocation of semiconductor device
US10234629B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2018 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | May 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and a method for producing a semiconductor device are disclosed. The semiconductor device includes a first silicon layer; a first dielectric layer, located on the first silicon layer, where the first dielectric layer includes a window, and a bottom horizontal size of the window of the first dielectric layer is not greater than 20 nm; and a III-V semiconductor layer, located on the first dielectric layer and in the window of the first dielectric layer, and connected to the first silicon layer in the window of the first dielectric layer. A III-V semiconductor material of the semiconductor device has no threading dislocations, and therefore has relatively high performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.