Dual loop adaptive LDO voltage regulator
US10234883B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Dec 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/614
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A voltage regulator circuit is disclosed. In one embodiment, a low drop-out (LDO) voltage regulator includes a voltage loop and a current loop. The current loop includes a source follower coupled to an output node of the LDO voltage regulator, the source follower being implemented with a PMOS transistor. The current loop also includes a current mirror coupled between a first branch of the current loop and a second branch of the current loop. The source follower is implemented in the second branch of the current loop. The voltage loop includes an amplifier circuit having an inverting input coupled to the output node, and a non-inverting input coupled to receive a reference voltage. The output of the amplifier is coupled to the gate terminal of the PMOS transistor of the current mirror.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.