Memory device capable of quickly repairing fail cell
US10235258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2015 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Feb 26, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.