Application specific integrated circuit interconnect
US10235488B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2018 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Jan 19, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for providing Chronos Channel interconnects in an ASIC are provided. Chronos Channels rely on a reduced set of timing assumptions and are robust against delay variations. Chronos Channels transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic. Chronos Channels are insensitive to all wire and gate delay variations, but for those belonging to a few specific forking logic paths called isochronic forks. Chronos Channels use temporal compression in internal paths to reduce the overheads of QDI logic and efficiently transmit data. Chronos Channels are defined by a combination of a DI code, a temporal compression ratio and hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.