Memory element write-assist circuitry with dummy bit lines
US10236055B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2015 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Mar 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with memory elements are provided. In particular, a group of random-access memory cells may be coupled to first and second data lines via corresponding access transistors. One of the first and second data lines can be driven to a ground voltage level to write a zero or one into a selected memory cell in the group. A first dummy data line can be formed adjacent to the first data line, whereas a second dummy data line can be formed adjacent to the second data line. During data loading operations, at least one of the dummy data lines can be pulsed to temporarily drive the voltage on the associated data line to below the ground voltage level. Operated in this way, the write operation of the memory cells can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.