Split memory bank
US10236063B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | May 22, 2018 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | May 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.