Display device and method for manufacturing the same
US10236330B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 2017 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Feb 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
Abstract
A plurality of thin film transistors provided in a peripheral region are first staggered thin film transistors where a first channel layer configured of low-temperature polysilicon is included, and the first channel layer is not interposed between a first source electrode and a first gate electrode, and between a first drain electrode and the first gate electrode. A plurality of thin film transistors provided in a display region are second staggered thin film transistors where a second channel layer configured of an oxide semiconductor is included, and the second channel layer is not interposed between a second source electrode and a second gate electrode, and between a second drain electrode and the second gate electrode. The first thin film transistor is located below the second thin film transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.