Multilayer electronic structures with embedded filters
US10236854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2018 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Apr 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a composite electronic structure for coupling an IC Chip to a substrate, the composite electronic structure comprising: at least one metal feature layer and at least one adjacent metal via layer, said layers being embedded in a dielectric comprising a polymer matrix and extending in an X-Y plane and having height, wherein the composite electronic structure further comprises, at least one capacitor coupled with at least one inductor, the at least one capacitor comprising a selected feature in a feature layer forming a lower electrode, and depositing a ceramic dielectric layer over said selected feature, applying a layer of photoresist, patterning the photoresist with a via post over said ceramic dielectric layer, sputtering a copper seed layer and electroplating copper into the pattern to form said via post over said ceramic dielectric layer, such that the ceramic dielectric layer is sandwiched between the selected feature layer and the via post, such that the via post stands on the ceramic dielectric layer, and forms an upper electrode whose capacitance is proportional to the area of the via post forming the upper electrode, and wherein the at least one indu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.