Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops
US10236895B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2017 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Dec 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.