Loss of lock detector
US10236897B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2018 |
| Grant date | Mar 19, 2019 |
| Priority date | — |
| Expiry date | Jul 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A loss of lock detection circuit includes detection circuitry and pulse accumulation circuitry. The detection circuitry includes a first flip-flop, a second flip-flop, and a third flip-flop. The first flip-flop is configured to synchronize a data stream to a first edge of a clock signal. The second flip-flop is configured to synchronize the data stream to a second edge of the clock signal. The third flip-flop is clocked by the data stream, and is configured to store a combined output of the first flip-flop and the second flip-flop at an edge of the data stream. The pulse accumulation circuitry is coupled to the detection circuitry. The pulse accumulation circuitry is configured to collect pulses generated by the third flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.