Patent · US Active

Autonomously controlling a buffer of a processor

US10241556B2 · kind B2 · utility

0Cited by
8References
19Claims
0Family size

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Key dates

Filing dateNov 27, 2013
Grant dateMar 26, 2019
Priority date
Expiry dateDec 7, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C2207/105
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O buffer to detect a value on the pad and to control the I/O buffer to provide the value to the pad, responsive to entry into an architectural state. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.