Memory subsystem to augment physical memory of a computing system
US10241906B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2016 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Nov 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for implementing a memory subsystem to augment physical memory of a computing system. For example, a system comprises a memory subsystem, and a computing system coupled to the memory subsystem. The computing system comprises a processor, a first memory module, and a second memory module. The first memory module comprises random access memory which is utilized by the processor to store data associated with an application executing on the computing system. The second memory module comprises control logic circuitry that is configured to control access to the memory subsystem on behalf of the processor to store and retrieve data associated with the application executing on the computing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.