Patent · US Active

Systems and methods for asymmetric memory access to memory banks within integrated circuit systems

US10241941B2 · kind B2 · utility

9Cited by

5References

20Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Joachim Fader · Munich, DE
Stephan Herrmann · Borgo San Lazzaro, DE
Amit Jindal · Palo Alto, US
Nitin Singh · Bengaluru, IN

Key dates

Filing date	Jun 29, 2015
Grant date	Mar 26, 2019
Priority date	—
Expiry date	Feb 29, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/4068
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.