Throttling integrated link
US10241952B2 · kind B2 · utility
0Cited by
25References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2015 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Feb 13, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.