Display control device and display panel module
US10242632B2 · kind B2 · utility
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1References
16Claims
0Family size
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Key dates
| Filing date | Jul 14, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Aug 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0666
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A halt period is inserted between a drive period in an odd-numbered field and a drive period in an even-numbered field in interlace driving. When drive signals driving subpixels are time-divisionally supplied to the display panel in units of subpixel types, switch control signals controlling source line switches which distribute the drive signals associated with respective subpixels to the corresponding source lines are generated so that the number of switching of the source line switches are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.