Highly compact floating gate analog memory
US10242991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2017 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Jun 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for forming a floating gate memory cell includes: forming an active region on a semiconductor substrate; forming a gate stack on the active region, the gate stack including a first gate layer defining a floating gate of the memory cell structure, a dielectric layer formed on the first gate layer, and a second gate layer defining a control gate of the memory cell structure formed on the dielectric layer; forming first and second source/drain regions in the active region, self-aligned with the gate stack; forming an erase/injection gate on at least a portion of the dielectric layer and spaced laterally from the control gate, the erase/injection gate being proximate to and above the floating gate; and forming multiple contacts providing electrical connection with the first and second source/drain regions, the control gate and the erase/injection gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.