Bias control for stacked transistor configuration
US10243519B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2016 |
| Grant date | Mar 26, 2019 |
| Priority date | — |
| Expiry date | Sep 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.