Integrated circuit with spare cells

US10243559B2 · kind B2 · utility

Assignee

• NXP USA, Inc. · US

Inventors

• Andreas Stahl · Cologne, DE
• Hubert M. Bode · Haar, DE
• Ilhan Hatirnaz · Munich, DE

Key dates

• Filing date: Mar 17, 2017
• Grant date: Mar 26, 2019
• Expiry date: Jun 15, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/975
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The disclosure relates to an integrated circuit comprising: a first voltage terminal; a second voltage terminal; and a plurality of logic cells, comprising one or more field effect transistors having a p-type channel and one or more field effect transistors having an n-type channel. The plurality of logic cells comprises a regular subset of cells and a spare subset of cells. Electrical connectors are arranged to: connect the gates of the regular subset of cells in order to provide a functional logic arrangement; connect the gates of the one or more field effect transistors having a p-type channel of the spare subset of cells to the first voltage terminal; and connect the gates of the one or more field effect transistors having an n-type channel of the spare subset of cells to the second voltage terminal.