Architectures and techniques for providing low-power storage mechanisms
US10248343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2016 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Nov 21, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.