Method and circuit for protecting and verifying address data
US10248580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2016 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Apr 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit is for protecting memory address data. The circuit may include an input data bus configured to receive write data to be written to a memory device, and an address bus configured to receive a corresponding write address. The circuit may also include an output data bus, and an address protection circuit coupled to the input data, address, and output data buses and configured to generate an address protection value based on the corresponding write address, and generate modified write data, on the output data bus. The modified write data includes the write data and the address protection value. The output data bus may have a width greater than a width of the input data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.