Controller circuit and method for estimating transmission delay
US10248608B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Dec 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller circuit includes a first signal processing device processing signals in accordance with a first predetermined rule, a second signal processing device processing signals in accordance with a second predetermined rule, a data bus coupled between the first signal processing device and the second signal processing device and comprising multiple data lines, and a confirm signal line coupled between the first signal processing device and the second signal processing device. The first signal processing device transmits a synchronization signal to the second signal processing device via the data bus. The second signal processing device estimates transmission delay on each data line according to the synchronization signal, performs transmission delay compensation on each data line according to the estimated transmission delay and transmits a confirmation signal on the confirm signal line to notify the first signal processing device that the transmission delay compensation is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.