Power savings method in a clock mesh-based design through a smart decloning technique
US10248750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2016 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Jul 10, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one general aspect, a method may include receiving a digital circuit model. The digital circuit model may include models of a clock mesh configured to provide a clock signal to a plurality of logic circuits, and a plurality of logic circuits, each logic circuit at least partially controlled by an application of the clock signal to one or more clock-gater cells. The method may include identifying a group of clock-gater cells having common input signals. The method may include calculating at least one clustered sub-portion of the group of clock-gater cells based upon a set of bounding dimensions, wherein each clustered sub-portion includes a plurality of clock-gater cells. The method may further include, for each clustered sub-portion, de-cloning in the digital circuit model the clock-gater cells by reducing the clock-gater cells to a new clock-gater cell and replacing the each clock-gater cell with a matching buffer cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.