Patent · US Active

Hardened white box implementation 2

US10249220B2 · kind B2 · utility

1Cited by

0References

17Claims

0Family size

Assignee

GIESECKE+DEVRIENT MOBILE SECURITY GMBH · DE

Inventors

Hermann Drexler · Munich, DE
Sven Bauer · Vaterstetten, DE
Jürgen Pulkus · Hersbruck, DE

Key dates

Filing date	Oct 30, 2015
Grant date	Apr 2, 2019
Priority date	—
Expiry date	May 22, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/16
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A processor device has an executable implementation of a cryptographic algorithm implemented being white-box-masked by a function f. The implementation comprises an implemented computation step S by which input values x are mapped to output values s=S[x], and which is masked to a white-box-masked computation step T′ by means of an invertible function f. As a mapping f there is provided a combination (f=(c1, c2, . . . )*A) of an affine mapping A having an entry width BA and a number of one or several invertible mappings c1, c2, . . . having an entry width Bc1, Bc2, . . . respectively, wherein BA=Bc1+Bc2+ . . . . Output values w are generated altogether by the mapping f. Multiplicities of sets Mxi, i=1, 2, . . . =Mx11, Mx12, . . . Mx21, Mx22, . . . are formed from the output values a of the affine mapping A.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.