GOA circuit
US10249243B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Apr 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a GOA circuit. The GOA circuit of the present invention comprises a plurality of GOA circuit units which are cascade coupled, wherein n is set to be a natural number larger than 0, and the nth level GOA circuit unit comprises: a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a fifth thin film transistor (T5), a sixth thin film transistor (T6), a seventh thin film transistor (T7), an eighth thin film transistor (T8), a ninth thin film transistor (T9), a tenth thin film transistor (T10), a first capacitor (C1) and a second capacitor (C2). Moreover, two control signals (Select1, Select2) are introduced. The present invention provides a new GOA circuit. The circuit possesses MLG function, which can effectively reduce the feedthrough and improve the Vcom uniformity in the panel to promote the quality of the image display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.