Semiconductor device
US10249708B2 · kind B2 · utility
2Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Oct 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.