FET with micro-scale device array

US10249711B2 · kind B2 · utility

Assignee

• TELEDYNE SCIENTIFIC & IMAGING, LLC · US

Inventors

• Keisuke Shinohara · Thousand Oaks, US
• Miguel Urteaga · Moorpark, US
• Casey King · Austin, US
• Avijit Bhunia · Newbury Park, US
• Ya-Chi Chen · New Taipei, TW

Key dates

• Filing date: Jun 29, 2017
• Grant date: Apr 2, 2019
• Expiry date: Jun 29, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.