Semiconductor device and method of manufacturing semiconductor device
US10249720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Mar 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/118
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
At edge termination region, a trench is disposed near an interface of an active region. Inside the trench, an embedded insulating film is embedded, and inside the embedded insulating film, a FP long in a direction of depth is disposed. The FP curves outwardly away from an inner side wall of the trench as a depth from a base front surface increases. At least near a bottom end of the FP, a distance between the FP and the inner side wall of the trench is greater than a width of the groove. The FP is connected to a front surface electrode that extends on the embedded insulating film. As a result, breakdown voltage may be enhanced, adverse effects of the surface charge may be reduced, and chip size may be further reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.