Multiple-stage power amplifiers implemented with multiple semiconductor technologies
US10250197B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Nov 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiple-stage amplifier includes a driver stage die and a final stage die. The final stage die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a first transistor. The driver stage die includes another type of semiconductor substrate (e.g., a silicon substrate), a second transistor, and one or more secondary circuits that are electrically coupled to a control terminal of the first transistor. A connection (e.g., a wirebond array or other DC-coupled connection) is electrically coupled between an RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die. The secondary circuit(s) of the driver stage die include a final stage bias circuit and/or a final stage harmonic control circuit, which are electrically connected to the final stage die through various connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.