Beta equalization to reduce non-linear distortions of bipolar transistor amplifiers
US10250211B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 9, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Nov 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Reducing non-linear distortions of an electronic device by performing at least the following: receiving, at an output stage circuit of an amplifier, an input signal from a previous stage circuit of the amplifier, driving a first subset of output transistors within the output stage circuit with an auxiliary buffer circuit to generate a first half cycle of an output signal Vout, driving a second subset of output transistors within the output stage circuit with the input signal to generate the first half cycle of the output signal Vout, and driving a set of output transistors with the input signal to generate a second half cycle of the output signal Vout, wherein the auxiliary buffer circuit equalizes the overall current gain associated with the first and second subset of output transistors with the overall current gain associated with the set of output transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.