Clock sustain in the absence of a reference clock in a communication system
US10250376B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2017 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Aug 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R2499/13
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.