Flexible buffer allocation in a network switch
US10250530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2016 |
| Grant date | Apr 2, 2019 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9005
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Communication apparatus includes multiple interfaces configured to be connected to a packet data network for receiving and forwarding of data packets of multiple types. A memory is coupled to the interfaces and configured as a buffer to contain packets received through the ingress interfaces while awaiting transmission to the network via the egress interfaces. Packet processing logic is configured to maintain multiple transmit queues, which are associated with respective ones of the egress interfaces, and to place both first and second queue entries, corresponding to first and second data packets of the first and second types, respectively, in a common transmit queue for transmission through a given egress interface, while allocating respective spaces in the buffer to store the first and second data packets against separate, first and second buffer allocations, which are respectively assigned to the first and second types of the data packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.