Patent · US Active

Addressable test chip test system

US10254339B2 · kind B2 · utility

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0References

19Claims

0Family size

Assignee

SEMITRONIX CORPORATION

Inventors

Fan Lan · Shanghai, CN
Shenzhi Yang · Yorktown Heights, US
Yongjun Zheng · Fuzhou, CN
Weiwei Pan · Taiyuan, CN

Key dates

Filing date	Dec 29, 2017
Grant date	Apr 9, 2019
Priority date	—
Expiry date	Dec 29, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

To improve test efficiency of addressable test chips, an addressable test chip test system includes a test equipment, a probe card and an addressable test chip, the test equipment connects to the addressable test chip through the probe card to constitute a test path, the test system includes a new type of address register, which can provide two test modes for users according to user's needs. A new type of high density addressable test chip can accommodate DUTs of more than 1000/mm2.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.