Array substrate motherboard, display panel motherboard, and fabricating method thereof
US10254602B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 7, 2016 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Dec 2, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2300/0413
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In some embodiments, an array substrate motherboard and a fabricating method thereof are provided. The method includes: providing a substrate including multiple gate lines, gate driving leads, data lines, and data driving leads, each gate line corresponds to one gate driving lead, each data line corresponds to one data driving lead; forming multiple gate line testing leads, each gate line testing lead is connected with a gate driving lead; forming multiple data line testing leads, each data line testing lead is connected with a subset of the multiple data driving leads; forming multiple gate line testing pads, each gate line testing pad is connected with a gate line testing lead; forming multiple data line testing pads, each data line testing pad is connected with two data line testing leads; and using the gate line testing pads and gate line testing pads to test the gate lines and data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.