Unified multiply unit
US10255041B2 · kind B2 · utility
2Cited by
11References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Jun 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/487
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed pertain to apparatuses, systems, and methods for performing multi-precision single instruction multiple data (SIMD) operations on integer, fixed point and floating point operands. Disclosed embodiments pertain to a circuit that is capable of performing concurrent multiply, fused multiply-add, rounding, saturation, and dot products on the above operand types. In addition, the circuit may facilitate 64-bit multiplication when Newton-Raphson, divide and square root operations are performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.