Microcontroller with variable length move instructions using direct immediate addressing or indirect register offset addressing
US10255073B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | May 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.