Adaptive CPU NUMA scheduling
US10255091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2014 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Nov 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for performing selection of non-uniform memory access (NUMA) nodes for mapping of virtual central processing unit (vCPU) operations to physical processors are provided. A CPU scheduler evaluates the latency between various candidate processors and the memory associated with the vCPU, and the size of the working set of the associated memory, and the vCPU scheduler selects an optimal processor for execution of a vCPU based on the expected memory access latency and the characteristics of the vCPU and the processors. The systems and methods further provide for monitoring system characteristics and rescheduling the vCPUs when other placements provide improved performance and efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.