Multichip debugging method and multichip system adopting the same
US10255150B2 · kind B2 · utility
1Cited by
9References
15Claims
0Family size
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Key dates
| Filing date | Dec 14, 2016 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Mar 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54446
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are a multichip debugging method and a multichip system adopting the same. The multichip system includes: a first chip including a first debugging port and first identification (ID) information, a second chip including a second debugging port and second ID information, and a test access port (TAP) electrically connected to the first debugging port and the second debugging port and configured to connect to a test apparatus via the TAP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.