Adapter device for large address spaces
US10255213B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2016 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | May 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are methods and adapter devices for buffering write transactions directed to a large space. In various implementations, an adapter device may include a sequential address buffer and a memory. A region of the memory may be configured as a data block, which may be associated with an address range. The address range may correspond to a region of an address space of a target device. The adapter device may be configured to receive a write transaction, the write transaction having an address and data. The adapter device may further write the address to the sequential address buffer. The adapter device may further determine that the address is within the address range, and to write the data to the data block. The adapter device may further, upon the occurrence of an event, write the data from the data block to the region of the address space of the target device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.