Secure computer architecture
US10255463B2 · kind B2 · utility
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30References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2008 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Dec 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A secure computer architecture is provided. With this architecture, data is received, in a component of an integrated circuit chip implementing the secure computer architecture, for transmission across a data communication link. The data is converted, by the component, to one or more first fixed length frames. The one or more first fixed length frames are then transmitted, by the component, on the data communication link in a continuous stream of frames. The continuous stream of frames includes one or more second fixed length frames generated when no data is available for inclusion in the frames of the continuous stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.