Systems and methods for determining clock rates for communicating with processing devices
US10255464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Nov 28, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K19/0701
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A payment terminal such as a payment reader may receive and form electrical connections with an electronic transaction card such as an EMV chip card. The payment terminal may provide a clock signal at a rate that exceeds a specified rate for the EMV chip card. The payment terminal may transmit messages to the EMV chip card and monitor receive messages at a data connection. The payment terminal may determine that the clock rate is excessive based on a timeout of a receive message, an error rate of a receive message, or a receive message indicating that one of the transmit messages was not received by the EMV card. The payment terminal may reduce the clock rate to a rate that is below the specified rate for the EMV chip card.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.