Mixed-signal circuitry for computing weighted sum computation
US10255551B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 7, 2018 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Feb 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and method are provided for performing weighted sum computations. The circuit includes: a plurality of current generators interconnected and arranged into pairs, a positive summation node, a negative summation node, and an input generation circuit. For each pair of current generators, the control terminal of each element is electrically connected to an input node. One of the current generators has its drain connected to the positive summation node while the other current generation element has its drain connected to the negative summation node. The remaining terminals on both current generators are connected to a reference, which may be shared. Each pair of current generator source predetermined amounts of current onto the two summation nodes when the following conditions occur: the input node is at an activation voltage, and the two summation nodes are at a predetermined target voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.