Gate driving circuit, array substrate, display panel and driving method thereof
US10255861B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jan 3, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Jan 3, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0291
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driving circuit is disclosed which includes n stages that are sequentially arranged, n being an integer larger than or equal to 4. The n stages are divided into a first, second, third and fourth sets of stages that are configured to receive respective different combinations of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal. The stages in the first set of stages and the stages in the third set of stages are cascaded with each other, and the stages in the second set of stages and the stages in the fourth set of stages are cascaded with each other. Also disclosed are an array substrate including the gate driving circuit, a display panel including the array substrate, and a driving method of the display panel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.