Accidental fuse programming protection circuits
US10255982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a fuse programming transistor, a cascode transistor, and a fuse cell electrically connected in series between a first pad and a second pad. The fuse system further includes a bias generator that controls an amount of current provided to the fuse cell based on biasing a gate of the fuse programming transistor and a gate of the cascode transistor. The fuse system further includes a fuse protection capacitor electrically connected between the first pad and the gate of the cascode transistor to prevent inadvertent programming of the fuse cell in response to an increase in voltage of the first pad relative to the second pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.