Methods and systems of impedance source semiconductor device protection
US10256626B2 · kind B2 · utility
3Cited by
18References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2016 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Apr 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/005
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electrical network configured to suppress voltage transients includes a capacitor and an electrical impedance in parallel with a diode. The capacitor is in series with the parallel connected diode and electrical impedance. The electrical network is configured to suppress voltage transients occurring across the series combination of the capacitor and the parallel connected diode and electrical impedance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.