Dual reset branch analog-to-digital conversion
US10256833B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2014 |
| Grant date | Apr 9, 2019 |
| Priority date | — |
| Expiry date | Jul 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.